1. Field of the Invention
The present invention relates to a mute (which is denoted as MUTE in the drawings) circuit for cutting off in an analog scheme an input signal, particularly relates to a zero-data-detection mute circuit of an output circuit of a one-bit D/A converter (hereafter referred to as D/A converter) using a ΣΔ modulator.
2. Description of the Related Art
FIGS. 20A and 20B show a circuit of an output section of a one-bit D/A converter using a ΣΔ modulator and a timing chart, respectively.
The output circuit section includes a ΣΔ modulator for receiving a multibit digital input, a digital to analog converter (D/A converter) for receiving a one-bit output of the ΣΔ modulator, and an inverting type operational amplifier (op-amp). An inverting input terminal (−) of the op-amp receives an analog output PRZ/ of the D/A converter via an input resistor, and a non-inverting input terminal (+) of the op-amp receives a reference voltage.
In the D/A converter, a function for detecting that input digital signals in a certain period are zero data and fixing the output voltage to a certain DC value (normally, midpoint potential) is frequently requested.
This is because, in the case of a D/A converter, another large-scale digital circuit is frequently provided on the same chip or same board in general and a large amount of unnecessary radiation is emitted to the D/A converter from the digital circuit as noises spatially or through a power source, thus deteriorating the performance of the D/A converter.
Moreover, in the one-bit D/A converter using the ΣΔ modulator, a converted output does not frequently become DC even if zero data is input and outputs waveforms containing a very-high-frequency noises referred to as requantization noises. Thus, uncomfortable sound is outputted or an undesirable S/N value may be obtained. To prevent these unwanted matters, zero-data-detecting mute technique is also used in the one-bit D/A converter using the ΣΔ modulator frequently.
In the ordinary zero-data-detecting mute system, that zero data are successively inputted for a certain period (normally, approximately. 100 msec) is detected and the analog output of the D/A converter is fixed to a reference potential.
Since the reference potential is normally decoupled by a capacitor having a large capacitance, noises that enter into the D/A converter is not so much. Hence, it is possible to prevent uncomfortable sound from being outputted and the S/N value from being deteriorated.
In the circuit in FIG. 23, since the filter amplifier of the D/A converter output section is an inverting type amplifier, then the mute is on (denoted as ON in FIG. 23) or off (denoted as OFF in FIG. 23) by turning on/off a feedback signal with an analog switch (hereafter referred to as switch) SW.
The circuit in FIG. 23 includes an adder for adding a multibit digital input and a digital DC offset, a ΣΔ modulator for receiving an output of the adder, a D/A converter for receiving a one-bit output of the ΣΔ modulator, an adder for adding an output of the D/A converter and an analog DC offset, a 0-data detecting circuit for receiving the multibit digital input, a switch SW controlled by an output of the zero-data (0-data) detecting circuit, and an inverting type operational amplifier (op-amp). The switch SW and a feedback resistor are connected in parallel to each other between an inverting input terminal (−) of the op-amp and output terminal of the op-amp. The inverting input terminal (−) of the op-amp receives an output signal of the adder for adding an output of the D/A converter and the analog DC offset via an input resistor, and a non-inverting input terminal (+) of the op-amp receives a reference voltage.
In this case, there is a large problem to operate a zero-data detecting mute, that is, a problem that a pop noise is generated when the mute is turned on/off. This is a pop noise generated due to that the DC value when a mute is turned on differs from the DC value when a mute is turned off. There are various causes of the problem as described blow.
To prevent a fixed pattern peculiar to a ΣΔ modulator and harmful beat noise from being generated, it is frequent to previously add digital DC offsets to an input signal of the ΣΔ modulator (see FIG. 22). Due to the addition of the digital DC offsets, analog DC offsets corresponding to input digital DC offsets are outputted and a pop noise is generated when a mute is turned on/off.
To prevent the above problem, a method is used in which analog DC offsets for canceling digital DC offsets are added as shown in FIG. 23. However, the digital DC offsets cannot be completely cancelled because of device accuracy or device variation and thus, some DC offsets are left.
Another problem is a DC error of a D/A converter generated in a DC offset due to slowdown of a waveform or device variation of a D/A converter.
A further problem is that when the mute is carried out by short-circuiting a feedback resistance with an input-converted DC offset of an operational amplifier as shown in FIG. 24, a DC change of EOS occurs and a pop noise is generated when the mute is turned on/off in the case of an operational amplifier having a input-converted DC offset serving as the EOS.
Though the above causes can be reduced by improving a circuit configuration or device accuracy or suppressing device variation, it is impossible to completely eliminate these disadvantages. That is, a small DC change is inevitably produced by turning on/off a mute and a pop noise is produced.
Thus, to minimize the pop sound, it is proposed to change the feedback resistor to a resistance variable resistor, and stepwise decrease or increase the resistance of the resistance variable feedback resistor.
When it is assumed that a potential difference of EM is generated if mutes are turned on/off, a stepwise waveform is obtained and an audible pop noise is produced by simultaneously turning on/off the mutes with the switch SW as shown in FIG. 25.
As shown in FIG. 26, by stepwise changing voltages, pop noises can be inaudibly heard. In this case, the pop noises are decreased in intensity in 15 steps. By further increasing the number of steps to smoothly change the voltages, the pop noises are further decreased in intensity (see FIG. 27).
FIG. 13 shows a circuit of a D/A converter using a zero-data-detecting mute function in which the pop sounds are decreased in intensity. In this case, the output level m of a ΣΔ modulator generally ranges between 2 and 15.
The circuit in FIG. 13 includes a ΣΔ modulator for receiving a multibit digital input, an m-level D/A converter for receiving an m-level digital output of the ΣΔ modulator, a 0-data detecting circuit for receiving the multibit digital input, an n-bit up-down counter for receiving an output of the 0-data detecting circuit, an n-bit to 2n line decoder for receiving an n-bit output of the n-bit up-down counter, a feedback resistor for receiving 2n−1 outputs of the n-bit to 2n line decoder, while an inverting type operational amplifier (op-amp). The feedback resistor is connected between an inverting input terminal (−) of the op-amp and output terminal of the op-amp. The inverting input terminal (−) of the op-amp receives an analog output of the m-level D/A converter via an input resistor, and a non-inverting input terminal (+) of the op-amp receives a reference voltage.
The circuit in FIG. 14 is a circuit obtained by making the circuit in FIG. 13 more specific, in which m is equal to 2 and n is equal to 4.
The circuit in FIG. 14 includes a ΣΔ modulator 101 for receiving a multibit digital input, a 2-level D/A converter for receiving a one-bit output of the ΣΔ modulator 101, a 0-data detecting circuit 103 for receiving the multibit digital input, a 4-bit up-down counter 105 for receiving an output of the 0-data detecting circuit 103, an 4-bit to 16 line decoder 107 for receiving a bit output of the 4-bit up-down counter 105, a feedback resistor circuit 111 for receiving outputs of the 4-bit to 16 line decoder, and an inverting type operational amplifier (op-amp) 109. The feedback resistor 111 is connected between an inverting input terminal (−) of the op-amp and output terminal of the op-amp. The inverting input terminal (−) of the op-amp receives an analog output PRZ/ of the 2-level D/A converter via an input resistor, and a non-inverting input terminal (+) of the op-amp receives a reference voltage.
FIG. 15B shows an example of a concrete configuration of the feedback resistor circuit 111 in FIG. 14.
The feedback resistor circuit in FIG. 15B is formed of a variable resistance circuit. In the variable resistance circuit, n resistors each having a resistance value of r are connected in series to form a first series-resistor circuit (n being an integer of 2 or more and 15 in this example). Analog switches SW1 to SW14 are connected between one terminal of the series-resistor circuit and respective nodes of the resistors of the series-resistor circuit. The analog switches SW1 to SW14 are on/off controlled by control signals S1 to S14 to stepwise change a resistance value of the first variable resistance circuit from 0 to n·r in units of r. The one terminal of the series-resistor circuit is connected to an input terminal IN of the variable resistance circuit, and the other terminal of the series-resistor circuit is connected to an output terminal OUT of the variable resistance circuit.
A further analog switch SW15 is connected between the one terminal of the series-resistor circuit (i.e., input terminal IN of the variable resistance circuit) and the other terminal of the series-resistor circuit (i.e., output terminal OUT of the variable resistance circuit) and controlled by control signal S15 to make a short-circuit between the terminals.
With the analog switches SW1 to SW15 being controlled by control signals S1 to S15, the resistance value of the feedback resistor circuit changes stepwise from 0 to 15r in units of r. Moreover, as shown in FIG. 26, a DC change when a mute is turned on/off smoothly changes to weaken a pop noise.
FIG. 15A shows the feedback resistor circuit 111 alone of the D/A converter in FIG. 14. FIG. 15C shows an example of a concrete circuit diagram of one analog switch in the feedback resistor circuit 111 in FIG. 15B, in which the analog switch is formed of n channel transistors and p channel transistors.
FIG. 16 shows an example of the zero-data detection circuit 103 in the circuit of FIG. 14.
The zero-data detection circuit 103 includes a NOR gate circuit for receiving a multibit digital input, a D-type flip flop circuit for receiving an output of the NOR gate circuit, an N-bit counter for receiving an output of the D-type flip flop circuit, and an RS-type flip flop circuit for receiving an output of the N-bit counter at its set terminal and the output of the D-type flip flop circuit at its reset terminal.
FIG. 17B shows an example of the decoder 107 in the circuit of FIG. 14.
The decoder 107 receives output signals Q1 to Q4 of the 4-bit U/D counter and outputs control signals S1 to S15 to the feedback resistor circuit. The decoder 107 includes a plurality of logic circuit sections which receive output signals Q1 to Q4 of the 4-bit U/D counter to perform logic operations and a plurality of flip flop circuits which are controlled by output signals of the logic circuit sections.
FIG. 17A shows a block diagram of the decoder and the counter of the circuit in FIG. 14. FIG. 17C shows an example of a concrete circuit diagram of one flip flop circuit in the decoder 107 in FIG. 17B.
FIG. 18 is a truth table of the decoder 107 in FIG. 17B.
FIG. 19A is a block diagram of the up-down counter 105 of the D/A converter in FIG. 14. FIG. 19B shows an example of a concrete configuration of the up-down counter 105 of the D/A converter in FIG. 14.
The up-down counter 105 includes flip flop circuit sections and logic circuit sections. The up-down counter 105 receives clock signal CKUDi and up-down control signal U/Di, and outputs count signals Q1 to Q4 and clock signal CKUD.
FIGS. 21A and 21B show a timing chart of a zero-data-detection mute circuit (including the zero-data detecting circuit 103, counter 105, decoder 107 and variable resistance circuit 111 in FIG. 14).
When the counter 105 is at 0, the variable resistance shows 15r which is the normal state. When an D/A converter input is zero data for a certain time period, a zero-data-detecting circuit output ZD becomes H (a high level) and a U/Di input of the counter 105 becomes H. When the U/Di input becomes H, the counter 105 starts up-counting and the control signals S1, S2, S3, . . . supplied from the decoder 107 sequentially become H as the state of the counter 105 increases to 1, 2, 3, . . . .
Moreover, switches SW1, SW2, SW3, . . . corresponding to the controls signals S1, S2, S3, . . . are turned on and the variable resistance decreases to 14r, 13r, 12r, . . . . Finally, the control signal S15 becomes H and the variable resistance is short-circuited (the state of the counter 105 becomes 15), and a mute is turned on.
However, when the D/A converter input is not zero data, the ZD instantaneously becomes L and the U/Di input of the counter 105 becomes L. When the U/D input becomes L, the counter 105 starts down-counting. As the state of the counter 105 increases to 14, 13, 12, . . . , control signals S14, S13, S12, . . . supplied from the decoder 107 sequentially become H.
Switches SW14, SW13, SW12, . . . corresponding to the signals S14, S13, S12, . . . are turned on and the variable resistance increases to r, 2r, 3r . . . . Finally, the state of the counter 105 becomes zero, every analog switch is turned off, the variable resistance becomes 15r which is the normal value, and the mute is turned off.
To minimize a pop noise as much as possible, as is clear by comparing FIG. 26 to FIG. 27, it is necessary to further increase the number of bits of the counter 105 and further smooth the waveform when the mute is turned on/off.
It is attempted here to consider doubling the number of change steps of the feedback resistance in the circuit in FIG. 15B. A circuit of the feedback resistance in such a case becomes a circuit shown in FIG. 28A in which 31 control signals S1 to S31 are used and thus it is found that the circuit scale is doubled. FIG. 28A shows a circuit configuration of a feedback resistor circuit in which the number of change steps is doubled to that of the feedback resistance in FIG. 15B and the circuit scale of the feedback resistor circuit is doubled to that of the feedback resistance in FIG. 15B, and FIG. 28B is a circuit configuration of one of the switches in the circuit in FIG. 28A.
Moreover, the decoder becomes that shown in FIG. 29B in which 31 control signals S1 to S31 are outputted and thus it is found that the circuit scale is doubled.
The decoder shown in FIG. 29B receives output signals Q1 to Q6 of the U/D counter and outputs control signals S1 to S31 to the feedback resistor circuit. The decoder includes a plurality of logic circuit sections which receive output signals Q1 to Q6 of the U/D counter to perform logic operations and a plurality of flip flop circuits which are controlled by output signals of the logic circuit sections. FIG. 29A shows a block diagram of a decoder in which the number of DC change steps is doubled to that of the conventional circuit in FIG. 17B, FIG. 29B is a concrete circuit configuration of the decoder in FIG. 29A, in which the circuit scale is doubled to that of the decoder in FIG. 17B, and FIG. 29C is a circuit configuration of a flip flop circuit in the decoder shown in FIG. 29B.
The counter does not become so large. However, when the circuit scale of the feedback resistance and the decoder is doubled, the whole circuit scale becomes significantly large. Moreover, by making the number of steps fourfold, the circuit scale of the feedback resistance and the decoder becomes fourfold and the load is greatly increased.
Moreover, when forming the circuit into an IC pattern, 31 resistances are connected in series in the case of n=5 as shown in FIG. 28A, and 32 contact portions (contact resistances) for connecting resistances with wiring are connected in series. Although a contact resistance value is made considerably small compared to that of a resistance body, it cannot be ignored when the number of contact portions for connecting resistances with wiring increases.
The voltage dependency or process variation of the contact resistance is not greatly considered in many cases differently from the case of the resistance body. As a result, the characteristic is deteriorated due to the voltage dependency of the contact resistance. Moreover, the gain of the D/A converter greatly varies due to the process variation of the contact resistance value.
To solve the above problems, a following method is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-77694.
FIG. 30B shows a configuration of the feedback resistor disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-77694. The general circuit of the output section of the D/A converter is the same as that in FIG. 14. The circuit in FIG. 30B is different from that in FIG. 15B in that a resistor r connected to the terminal IN is added. Moreover, when switches SWL1, SWL2, and SWL3 controlled in accordance with control signals SL1, SL2, and SL3 are turned on/off, resistors 3r, r, and r/3 each are connected in parallel to the added resistor r in the variable feedback resistance circuit. Furthermore, the resistor r connected between the switch SW14 controlled in accordance with the control signal S14 and the switch SW15 controlled in accordance with the control signal S15 is eliminated.
With the modification above, the resolution is expanded by 2 bits. That is, by increasing or decreasing the variable resistance of the feedback resistor circuit in units of r/4, instead of increasing or decreasing the variable resistance of the feedback resistor circuit in units of r, it is possible to further smooth the voltage change and decrease the pop noise.
The control signals SL1 to SL3 are signals constituted by the LSB (Least Significant Bit) and its one digit upper bit of an output of a counter. The switches SWL1 to SWL3 are controlled by control signals SL1 to SL3 so that the resistance value between the IN terminal and the common node of the switches SW1 to SW14 controlled in accordance with control signals S1 to S14 becomes r when the LSB and its one digit upper bit of the counter are (0, 0), 3r/4 when these bits are (1, 0), r/2 when these bits are (0, 1), and r/4 when these bits are (1, 1).
In this way, when the state of the counter changes to 0, 1, 2, . . . , 58, 59, 60, 61, 62, and 63, the feedback resistance value changes to 15r, 14.75r, 14.5r, . . . , 0.5r, 0.25r, 0, 0, 0, and 0. Thus, it is found that the number of change steps in the feedback resistance circuit of FIG. 30B becomes approximately fourfold as shown in FIGS. 33A and 33B compared to the number of change steps in the feedback resistance circuit of FIG. 15B. As to the circuit scale of the feedback resistance circuit, only the number of resistors r is increased by 3, the number of switches is increased by 3, and the number of control terminals is increased by 3.
FIG. 31B is a circuit of the decoder used with the feedback resistance circuit of FIG. 30B. FIG. 32B is a counter circuit used with the feedback resistance circuit of FIG. 30B. FIGS. 33A and 33B show a truth table of the decoder of FIG. 31B.
FIG. 34B is a modified circuit of FIG. 30B in which the switches each are formed of only an N-channel MOS transistor. As is known, since the on-resistance of MOS transistors is nonlinear, a distortion is normally generated in an output signal when MOS transistors are used.
However, in the case of this circuit, MOS transistors are used to provide the switches of a simple structure, rendering it possible to reduce the circuit scale, while considering that the switches are turned on only when the D/A converter input is zero data and the on-time is very short and transient.
Only the switch SW15 controlled in accordance with the control signal S15 for decreasing the feedback resistance to 0 (zero) is made of a combination of the P-channel MOS transistor and N-channel MOS transistor, as shown in FIG. 15C. This is because only the switch SW15 is not transiently turned on but it is continuously turned on while a mute operates. Therefore, it is prevented that a DC change does not occur even if a comparatively large noise is generated. It is naturally possible to use a P-channel transistor instead of an N-channel MOS transistor. In this case, it is necessary to invert a control signal.
In this way, by using the method disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-77694, it is possible to make the number of change steps of the feedback resistance fourfold, further smooth a DC-voltage change from mute-off to mute-on, and avoid an uncomfortable pop noise.
However, when a smoother DC change is further requested for HiFi use, it is requested that the number of change steps of a feedback resistance should be doubled. A circuit according to the requirement is as shown in FIG. 35B, when using the method disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-77694.
In the circuit in FIG. 30B, resistance r/4,r/2, and 3r/4 are obtained by providing resistors having resistance values r/3,r, and 3r in parallel with a resistor having a resistance value r. However, the circuit in FIG. 35B generates resistances r/8,r/4, 3r/8,r/2, 5r/8, 3r/4, and 7r/8 by providing resistors having resistance values r/7, r/3, 3r/5, r, 5r/3, 3r, and 7r in parallel with a resistor having a resistance value r.
Therefore, it is necessary to form a high-accuracy resistance resistor having resistance 7r, which is 49 times resistance r/7. Moreover, the total resistance value of this resistor section (resistors having resistances r/7, r/3, 3r/5, r, 5r/3, 3r, and 7r) becomes 13.7r. When this resistor structure is formed on an IC, the chip occupation area is considerably increased and the chip cost is increased. Moreover, since the area of a feedback resistance portion is increased, then noises incoming due to that the wirings function as antennas are increased and noises incoming from the contact area with the substrate are increased. Hence, the characteristic of the variable feedback resistance circuit is deteriorated.